1. Field of the Invention
This invention relates to digital-to-analog converters (DACs), and more particularly to DACs implemented as integrated circuits.
2. Description of the Prior Art
Numerous types of DACs have been designed which convert input digital signals to an output analog format. A basic type of DAC, referred to as a weighted R device, is shown in FIG. 1. It consists of a series of binarily weighted resistors which are connected in common to one side to an output line 2, each resistor comprising one step of the ladder. For n steps, the resistor in the circuit for the most significant bit (MSB) has a value R, while the resistor in the circuit for the least significant bit (LSB) has a value 2.sup.n-1 R. The resistance values for the intermediate bits are scaled binarily between the MSB and LSB. Each resistor can be connected by means of a switch 4 to either a ground line 6, or a common voltage reference line 8. For any given input signal, the step circuits corresponding to the input bits having a digital 1 are connected to the voltage reference line 8, while the step circuits corresponding to the bits having a digital 0 are connected to the ground line 6. In this way, an output signal equal to the weighted sum of the currents flowing through the various steps connected to the voltage reference line 8 will appear on output line 2. This signal is amplified and converted to an output voltage signal V.sub.0 by means of amplifier 10 having a feedback resistor R.sub.F.
While the weighted R circuit is simple in design, a large number of resistors are required to give it a useful range; the higher value resistors can become quite large and occupy undesirably amounts of area on the chip.
Another type of conventional DAC, referred to as an R-2R ladder device, is shown in FIG. 2. In this device the various steps have equal value 2R resistors. The input sides of the circuits are switched between a voltage reference line 8 and a ground line 6 by means of switches 4 in a manner similar to the weighted R device of FIG. 1. The output sides of successive steps, however, are connected to each other through additional resistors of resistance value R, with the output of the LSB connected to ground through a 2R resistor. An output analog voltage V.sub.0 is obtained from the output of the MSB through amplifier 10 with feedback resistor R.sub.F. The switch for the MSB step is controlled directly by the most significant bit of the input digital signal, the switch for the next most significant step is controlled by the second most significant bit of the input digital signal, and so forth.
A binary relationship is established between successive bits of the R-2R ladder circuit. While it is more economical for the number of resistors required than is the weighted R circuited of FIG. 1, it still requires switching between two definite voltage levels, and is subject to substantial temperature variations.
A different design, referred to as a segmented DAC, is shown in FIG. 3. Again, individual ladder steps circuits are switched between a voltage reference line 8 and a ground line 6. As in the designs of FIGS. 1 and 2, MOS switches are typically employed. The ladder steps each have the same resistance R, and are connected in parallel between the voltage reference/ground lines 8/6 and the output line 2. A very large number of step resistance circuits, equal to 2.sup.n-1, are used, where n is equal to the number of bits in the input digital signal. A decode logic circuit 12 is provided which converts the input digital signal, consisting of bits B1-Bn, into a control signal which connects the appropriate number of steps to the voltage reference line 8. For example, for an 8 bit input digital signal with 511 different possible values, 511 separate step circuits would be provided, and the number of steps connected to the voltage reference line at any time would equal the value of the input digital signal.
While more accurate than the weighted R or R-2R designs, the segmented DAC requires an extremely large number of resistors, which increases geometrically with the number of bits in the input digital signal. Also, because switching occurs over a relatively large voltage range between V.sub.REF and ground, switching is still relatively slow because of the capacitance associated with practical semiconductor switches.
A modification of the FIG. 3 approach which attempts to compensate for its slow switching speed is shown in FIG. 4. In this design the switches 4 are moved to the output side of the resistors, and therefore do not have to switch all the way between the voltage reference and ground. While this design offers some improvement and is in common use in many CMOS DACs, the capacitance associated with practical switches degrades the phase margin of the amplifier, leading to a requirement for extremely low capacitance switches to obtain high speed performance.
Bipolar transistor switches offer faster switching speeds than most MOS transistors because the bipolar devices are smaller. A conventional DAC design using bipolar transistors is shown in FIG. 5. A ladder network is provided with resistors having equal resistance values for a segmented device, or weighted resistance values for a weighted ladder; an R-2R ladder can also be used. The network is referenced to a negative voltage level obtained from the positive voltage reference line 8, via inverting amplifier 14. Transistor Q1 is a compensating element for transistors Q2-Q4, which provide current sources for accumulated an analog output. The resistor ladder network divides the currents through the transistors Q2-Q4 such that the current through each transistor is decremented by a predetermined portion of the current through the preceding transistor for a weighted ladder, or is equal to the other transistor currents for a segmented ladder. The base-emitter junctions of transistors Q1-Q4 are geometrically scaled in a weighted ladder to offset the effect of the different current levels, which otherwise would produce a different V.sub.be for each transistor.
Each of the bit transistors Q2-Q4 is supplied through a respective pair of bipolar switching transistors, with Q5 and Q6 supplying Q2, Q7 and Q8 supplying Q3, and Q9 and Q10 supplying Q4. The outputs of Q5, Q7 and Q9 are connected to ground and are actuated when no output is desired from their respective bits, while the outputs of Q6, Q8 and Q10 are connected to an output line 2.
Q1 compensates for the error associated with Q2-Q4, where .alpha. equals 1-1/.beta., and .beta. is the transistor current gain. Similarly, another bipolar transistor Q11 is provided between voltage reference line 8 and Q1 to compensate for the .alpha. error associated with Q6, Q8 and Q10. Any mismatches of .alpha. between the various transistors are not compensated, but can generally be overcome by trimming the resistors. However, since .alpha. is dependent upon .beta., and .beta. varies by a factor of about 1:3 over the military specification temperature range of -55.degree. C. to 125.degree. C., the .alpha. errors cannot be trimmed out over this temperature range. This can lead to serious operating problems, especially with DACs of over 12 bits. In some cases the transistor switches Q5-Q10 have been replaced with diode switches, but .beta. still has a significant temperature variation because the DAC currents still have to pass through transistors Q1-Q4.